Verus Research is searching for a Senior Digital Design Engineer to perform implementation of advanced FPGA/SoC design and algorithms.
The Senior Digital Design Engineer will make contributions to technical projects that require development and deployment of low-level algorithms into FPGAs. The candidate will be responsible for significant partitions of complex designs and must work effectively with other engineers. This is a senior algorithm development role and the ability to develop and debug RTL designs in simulation is essential. Familiarity with FPGA synthesis, constraints, timing closure, and hardware-software interfacing is expected. Verus Research is committed to solving our customer’s most challenging technical problems and seeks solution-oriented individuals to enhance our team’s ability to thrive in this role. This posting is for work in Albuquerque, NM.
The ideal candidate for the Senior Digital Design Engineer position will possess strong research and critical thinking skills, demonstrate an understanding of FPGA architecture and development, be able to communicate technical concepts clearly and concisely, both verbally and in writing, and thrive in a multi-disciplinary team environment. Success in this role will stem from:
• U.S. Citizenship
• Bachelor’s degree in electrical engineering or similar discipline
• Minimum five years demonstrated experience implementing domain algorithms in modern FPGAs in the areas of RF signal processing, control theory, networking, or cryptography
• Solid understanding of RTL (VHDL or Verilog) development utilizing simulation
• Experience with FPGA synthesis, including knowledge about clock crossing and FPGA timing, and using FPGA vendor simulation/design tools (Quartus, Vivado, QuestaSim, VCS, XCelium, Riveria, etc.)
• Knowledge of common FPGA communications methods and protocols such as Ethernet, I2C, SPI, CAN, APB, AXI/AXI-streaming, etc.
• Expertise in leveraging COTS SDK packages for implementing high TRL SOSA-compliant embedded hardware solutions